1. Field of the Invention
The present invention relates to a disk drive system for use, for example, in an FDD (floppy disk drive) apparatus.
2. Description of the Prior Art
FIG. 4 shows a block diagram of a conventional disk drive system designed for use in an FDD apparatus. In FIG. 4, near a spindle motor for rotating a disk, a coil L1 for reference position detection is arranged, of which both ends are connected to the input terminals of an index comparator 1. The index comparator 1 outputs a signal (hereafter referred to as the "index signal") I in which one pulse appears every time the spindle motor makes one complete turn.
This index signal I is fed out via a terminal TI, and is fed to a control circuit (not shown) that controls the operation of the various circuits constituting the FDD apparatus. Using the index signal I, the control circuit controls the timing with which data is written to and read from the disk.
Also arranged near the spindle motor is a coil L2 formed by a conducting pattern for rotation rate detection. This coil L2 generates a sine wave, which is converted by an FG comparator 2 into a square wave F (hereafter referred to as the "rotation rate detection signal") and then fed to the speed discriminator 7. In the rotation rate detection signal F, a plurality of pulses appear while the spindle motor makes one complete turn; the higher the rotation rate of the spindle motor, the shorter the period of the pulses, and the lower the rotation rate of the spindle motor, the longer the period of the pulses.
Around the rotor of the spindle motor are arranged Hall-effect devices H1, H2, and H3, which are connected to the input terminals of amplifiers 3, 4, and 5, respectively. The three output signals from these amplifiers 3, 4, and 5 are used as rotation position detection signals P that together indicate the rotational position of the spindle motor.
In accordance with the rotation position detection signal P, a drive circuit 6 switches with appropriate timing the current fed to the coils U, V, and W provided one for each of three phases in the spindle motor in such a way that the spindle motor rotates as efficiently as possible. Moreover, in accordance with the rotation rate error signal G described later that is fed from the speed discriminator 7, the drive circuit 6 determines the current fed to the coils of the spindle motor in such a way that the rotation rate of the spindle motor is kept at a predetermined rate.
FIG. 5 shows the configuration of the speed discriminator 7. As shown in FIG. 5, the speed discriminator 7 has a counter 71 and a comparison circuit 72. The counter 71 counts a predetermined period; specifically, it counts the period of the rotation rate detection signal F as observed when the rotation rate of the spindle motor is equal to the central value of the rated rotation rate range. The comparison circuit 72 receives the signal A.sub.1 output from the counter 71 and the rotation rate detection signal F, and compares the period of the rotation rate detection signal F with the period counted by the counter 71 so as to feed the drive circuit 6 with a rotation rate error signal G representing the difference between the periods of those two signals.
The speed discriminator 7 further has a counter 73 that counts a period shorter by t than the period counted by the counter 71. This counter 73, when triggered at a rising edge of the rotation rate detection signal F, turns its output to a low level and starts a counting operation, and, at the end of the counting operation, turns its output to a high level.
The signal A2 output from the counter 73 provided within the speed discriminator 7 is fed to a counter 8, which, when triggered at a rising edge of the signal A2, i.e. at the end of the counting operation of the counter 73, turns its output to a high level and starts its own counting operation, and, after counting a period of 2t, turns its output to a low level.
The signal B output from the counter 8 and the rotation rate detection signal F are fed to the data input terminal D and the clock input terminal CK, respectively, of a D flip-flop 9. The output terminal Q of this D flip-flop 9 is connected to a terminal TS. The signal output from the output terminal Q of the D flip-flop 9 is, as a status signal S, fed out of the disk drive system via the terminal TS.
FIG. 6 shows a timing chart of the relevant signals in this circuit configuration. Specifically, when the rotation rate of the motor is lower (or higher) than the rated rotation rate range, the rotation rate detection signal F turns from a low level to a high level after (or before) the signal B output from the counter 8 turns from a low level to a high level, and thus the status signal S is kept at a low level. By contrast, when the rotation rate of the motor is within the rated rotation rate range, the rotation rate detection signal F turns from a low level to a high level while the signal B output from the counter 8 is at a high level, and thus the status signal S is kept at a high level.
The status signal S is fed to the control circuit. When the status signal S turns to a high level, the control circuit recognizes that the current rotation rate of the disk is within the rated rotation rate range, and thus starts controlling data writing/reading operations against the disk.
Here, it is to be noted that, as shown in FIG. 7, immediately after the spindle motor has been started to rotate, its rotation rate first varies unstably, becoming sometimes higher and other times lower than the rated rotation rate range RS, before settling within that range RS.
In the conventional disk drive system, whether the rotation rate is within the rated rotation rate range or not is checked at a rising edge of the rotation rate detection signal F. Since the rotation rate detection signal F is a high-frequency signal whose frequency varies according to the rotation rate of the spindle motor, when the rotation rate of the spindle motor is unstable as when the spindle motor has just been started to rotate, the status signal S is likely to oscillate between a high and a low level at a high frequency (see FIG. 6). This causes malfunctioning of the FDD apparatus.
Instead, when the rotation rate of the motor is unstable, the status signal S is as likely to be unnecessarily kept at a high level. This causes data writing/reading operations against the disk to be performed while the rotation rate of the motor is unstable, and thus causes malfunctioning of the FDD apparatus due to the status signal S.
To prevent such malfunctioning of the FDD apparatus, the side that receives the status signal S (i.e. the control circuit in the example described above) needs to be provided with a special means for that purpose.